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RISC-V Group Lifecycle
RVG-83
Microarchitecture Side-Channel Resistant Instruction Spans (uSCR-IS) ❗️❗️❗️
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Details
Type:
Group
Resolution:
Unresolved
Priority:
Medium
Labels:
Group_Kick-off_Completed
RVI Staff Action:
Required
Group Type:
Task Group (TG)
Groups.io:
https://lists.riscv.org/g/tech-uscr-is
Charter:
https://github.com/riscv-admin/uscr-is
Is Acting Chair?:
Yes
Chair Affiliation:
INRIA
Vice-chair Affiliation:
ETH Zurich
Attachments
Issue Links
is direct-lined by
RVG-122
Unprivileged Spec (IC)
Active
is dotted-lined by
RVG-68
Security (HC)
Active
Activity
People
Assignee:
Unassigned
Reporter:
Rafael Sene
Votes:
0
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Watchers:
1
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Dates
Created:
14/Jul/23 8:09 PM
Updated:
26/Dec/23 6:41 PM