Zicond is a fast-track extension (approved in Q4CY2022 by the AR) to add two integer instructions that allow building up conditional-ops in a RISC-V compatible way:

• unconditional (not predicated) ALU operation (czero.eqz/czero.nez)
• Think of it as a special form of seqz/snez that sets the destination to “0” or a supplied register-value (instead of “0” or “1”).

• 1 destination operand, 2 source operands
• allows building up common conditional sequences:
• conditional-{add,subtract}, conditional-bitwise-{or,xor}: 2 insns
• conditional-bitwise-{and,select}: 3 insns (requires 1 temporary register)

• no new relocations, no new ABI changes required

Owner: Philipp Tomsich

Legacy documents:

• Plan milestone slides: https://docs.google.com/presentation/d/1vO9NmyEheYpPlbz4vDIlrALfKZxpSqjLVkI91wyroCE/edit#slide=id.g1db5ba545f4_0_0
• Status checklist: https://docs.google.com/spreadsheets/d/10uWgib-DFQ40WfaoWY9l521s3-Pn4Pp3hH0BgnSk8qY/