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Specification
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Resolution: Done
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Medium
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Yes
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ISA
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Zicond
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Ratification-Ready Approved
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Completed
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Completed
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Completed
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Approved
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0
Zicond is a fast-track extension (approved in Q4CY2022 by the AR) to add two integer instructions that allow building up conditional-ops in a RISC-V compatible way:
- unconditional (not predicated) ALU operation (czero.eqz/czero.nez)
- Think of it as a special form of seqz/snez that sets the destination to “0” or a supplied register-value (instead of “0” or “1”).
- 1 destination operand, 2 source operands
- allows building up common conditional sequences:
- conditional-{add,subtract}, conditional-bitwise-{or,xor}: 2 insns
- conditional-bitwise-{and,select}: 3 insns (requires 1 temporary register)
- no new relocations, no new ABI changes required
Owner: Philipp Tomsich
Legacy documents: