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  1. RISC-V Specification Lifecycle
  2. RVS-1017

Fast Interrupts (CLIC)

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    • FastInt
    • No
    • ISA
    • Smclic, Ssclic, Suclic, Smclicshv, Smclicconfig
    • Review Requested
    • Not Started
    • 3

      A low-latency, vectored, priority-based, preemptive interrupt scheme for interrupts directed to a single hart, compatible with the existing RISC-V standards.

      Author: Dan Smathers

      Legacy documents:

        1.
        		 [Freeze] - ARC Review (required) ARC Review Under AR Review Rafael Sene 31/Dec/23 0
        2.
        		 [Freeze] - Ensure Compliance with RISC-V Specification Policies Approval Not Started Jeff Scheel 31/Dec/23 0
        3.
        		 [Freeze] - Request Signoffs from Committee Chair Approval Not Started Jeff Scheel 31/Dec/23 0
        4.
        		 [Freeze] - Request Signoff from RISC-V CTO Approval Not Started Jeff Scheel 31/Dec/23 0

            Unassigned Unassigned
            jscheel Jeff Scheel
            Daniel Smathers Daniel Smathers
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              Created:
              Updated: