There is a growing need for a Zero-Trust architecture in HW, where a software application can both examine and attest to the environment it is running in, and have guarantees that it is isolated from other, untrusted software. The Trusted Computing SIG will examine the state of the art for hardware-assisted technologies such as Confidential Computing, Remote Attestation, Confidential VM, Hardware TEE, Enclaves, etc., on an ongoing basis,  and define the trusted computing strategy for RISC-V. It will develop TG Charters as required, that will define the required written documentation, threat models, executable model, prototype implementations including SW PoCs, toolchain support, and compliance suite for RISC-V trusted execution recommendations and extensions.

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