The Vector Special Interest Group (SIG) operates under the Unprivileged Committee and focuses on developing strategies, identifying gaps, and setting priorities for SIMD (Single Instruction, Multiple Data) processing capabilities within the RISC-V architecture. By SIMD processing capabilities, we mean the ability to store and manipulate collections of elements organized as vectors, matrices, tensors, and other related data structures.

The main objective of the Vector SIG is to establish RISC-V as the preferred architecture for SIMD processing across a broad range of applications, spanning from embedded systems to supercomputers. To achieve this, the Vector SIG will consistently work on enhancing the SIMD processing capabilities of the RISC-V architecture.

To enhance the SIMD processing capabilities, we will first identify gaps in the RISC-V Instruction Set Architecture and then recommend Task Groups responsible for specifying the required enhancements. These gaps will be prioritized, and a strategy will be devised to address them in the determined order of priority.

The RISC-V Vector SIG will propose a set of enhancements for SIMD processing in the RISC-V architecture. The actual specifications for these enhancements will be developed by the Task Groups formed based on the Vector SIG's recommendations. However, the final decision regarding the creation of Task Groups lies with the Technical Steering Committee.

The RISC-V Vector SIG will maintain ongoing collaboration with various groups within the RISC-V community, including Committees, SIGs, and TGs (Task Groups). Although the list of collaborators may change over time, initial collaborators will include the Vector TG (Zvfh extension), Packed SIMD TG (P extension), Graphics SIG, AI/ML SIG, Applications and Tools Committee, Vector Crypto TG, and Compiler Built-ins SIG.

Leadership History

Period	Chair	Vice-chair
2023-2024	José Moreira jmoreira@us.ibm.com	Abel Bernabeu abel.bernabeu@esperantotech.com