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Specification
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Resolution: Unresolved
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Medium
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SPMP
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No
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ISA
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Sspmp
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Review Requested
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Approved
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0
The SPMP TG develops the SPMP (S-mode Physical Memory Protection) extension for memory isolation on the low-end systems as an alternative to the paged virtual memory system. The SPMP TG will deliver an SPMP architectural specification, which includes access control of read/write/execute requests by an hart, exceptions for access violation, virtualization support, etc. Besides the specification, the SPMP Task Group will work with the Security HC and other committees/SIGs/TGs, and development partners to provide simulators (Spike and Qemu), Sail formal model, test cases, and reference code for commercial OSes (e.g., Linux and RTOS) and open-sourced hypervisors (e.g., KVM and Xvisor) for SPMP.
1.
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[Freeze] - Complete Documentation of New Instructions, State Changes, and ISA Alterations | In Progress | Unassigned | 31/Dec/23 | 1 | ||
2.
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[Freeze] - Implement Simulator Support | Not Started | Unassigned | 31/Dec/23 | 0 | ||
3.
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[Freeze] - Develop RISC-V Tests | In Progress | Unassigned | 31/Dec/23 | 1 | ||
4.
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[Freeze] - Perform Input Testing | Not Started | Unassigned | 31/Dec/23 | 0 | ||
5.
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[Freeze] - Add Support into the Sail Golden Model | In Progress | Unassigned | 31/Dec/23 | 0 | ||
6.
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[Freeze] - Create Proof of Concept | In Progress | Unassigned | 31/Dec/23 | 1 | ||
7.
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[Freeze] - ARC Review (required) | Under AR Review | Rafael Sene | 31/Dec/23 | 3 | ||
8.
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[Freeze] - Ensure Compliance with RISC-V Specification Policies | Not Started | Unassigned | 31/Dec/23 | 0 | ||
9.
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[Freeze] - Request Signoffs from Committee Chair | Not Started | Unassigned | 31/Dec/23 | 0 | ||
10.
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[Freeze] - Request Signoff from RISC-V CTO | Not Started | Unassigned | 31/Dec/23 | 0 |