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  1. RISC-V Specification Lifecycle
  2. RVS-913

Vector Crypto - all-rounds AES

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    • ISA
    • Zvknf
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      Zvknf - NIST Suite: Vector AES Encryption & Decryption (Full Rounds)

      Instructions for accelerating full-round encryption, decryption and key-schedule functions of the AES block cipher.
      To help avoid side-channel timing attacks, these instructions shall be implemented with data-independent timing.

      Plan: https://docs.google.com/document/d/1TitBSEIIwr2_JqUo21QxCLjd9Hw_3wK0Da4zfRtsnok/edit#heading=h.hym1mtuc89he

      GitHub Reference: https://github.com/riscv/riscv-crypto/blob/168e7b477d07c7f348809ae03588967a2bc04e25/doc/vector-allrounds/riscv-crypto-vector-zvknf.adoc#L1

       

       

        1.
        [Inception] - Infrastructure Setup Request Specification Acceptance Criteria Done Unassigned 03/Jul/23 0
        2.
        [Plan] - Develop Specification Plan Planning Acceptance Criteria Not Started Unassigned 10/Jul/23 0
        3.
        [Plan] - Governing Committee Approval Approval Not Started Unassigned 03/Jul/23 0
        4.
        [Plan] - Schedule Plan Presentation to Chairs Specification Acceptance Criteria Not Started Unassigned 03/Jul/23 0
        5.
        [Plan] - Present Plan to Chairs Specification Acceptance Criteria Not Started Unassigned 03/Jul/23 0
        6.
        [Plan] - Chairs Approval Approval Not Started Unassigned 03/Jul/23 0
        7.
        [Plan] - Notify TSC Specification Acceptance Criteria Not Started Unassigned 03/Jul/23 0

            Unassigned Unassigned
            rsene Rafael Sene
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              Created:
              Updated: