The Zvfhmin extension provides minimal support for vectors of IEEE 754-2008 binary16 values, adding conversions to and from binary32. When the Zvfhmin extension is implemented, the vfwcvt.f.f.v and vfncvt.f.f.w instructions become defined when SEW=16. The EEW=16 floating-point operands of these instructions use the binary16 format.
The Zvfhmin extension requires a standard vector extension with single-precision floating-point support (currently, Zve32f, Zve64f, Zve64d, or V).

 
The Zvfh extension provides support for vectors of IEEE 754-2008 binary16 values. When the Zvfh extension is implemented, all instructions in Sections Vector Floating-Point Instructions, Vector Single-Width Floating-Point Reduction Instructions, Vector Widening Floating-Point Reduction Instructions, Vector Floating-Point Move Instruction, Vector Floating-Point Slide1up Instruction, and Vector Floating-Point Slide1down Instruction become defined when SEW=16. The EEW=16 floating-point operands of these instructions use the binary16 format.
Additionally, conversions between 8-bit integers and binary16 values are provided. The floating-point-to-integer narrowing conversions (vfncvt[.rtz].x[u].f.w) and integer-to-floating-point widening conversions (vfwcvt.f.x[u].v) become defined when SEW=8.
The Zvfh extension requires a standard vector extension with single-precision floating-point support (currently, Zve32f, Zve64f, Zve64d, or V). The Zvfh extension additionally requires the Zfhmin extension.

GH Reference: https://github.com/riscv/riscv-v-spec/blob/d404111e51298b428f5bba6041d6288a6a209664/v-spec.adoc#zvfhmin-vector-extension-for-minimal-half-precision-floating-point-arithmetic