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  1. RISC-V Specification Lifecycle
  2. RVS-715

Zv* - Vector Crypto

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    • No
    • ISA
    • Zvbb, Zvbc, Zvkb, Zvkg, Zvkn, Zvknc, Zvkned, Zvkng, Zvknha, Zvkbnhb, Zvks, Zvksc, Zvksed, Zvksg, Zvksh, Zvkt
    • Fast-Track Approved
    • Ratification-Ready Approved
    • Completed
    • Approved
    • Completed
    • Completed
    • Completed
    • Completed
    • Approved
    • 0

      Describes the proposed vector cryptography extensions for RISC-V. All instructions proposed here are based on the Vector registers. The instructions are designed to be highly performant, with large application and server-class cores being the main target

      Ratification Plan: https://docs.google.com/document/d/1q7Z9Yn22udJAeLCZT7ipIB4pUvqDbWJ_6KUX-hdbJIo/edit
      Acceptance Criteria: https://docs.google.com/spreadsheets/d/1Trwd7mr91iKlOi7cVlmJaoulw1ZGAAYR8ER7-pRufyI/edit#gid=1751770475

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            Unassigned Unassigned
            rsene Rafael Sene
            Ken Dockser Ken Dockser
            Ken Dockser Ken Dockser
            Ken Dockser Ken Dockser
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              Created:
              Updated:
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