The IOMMU architecture specification defines a unified IOMMU appropriate for RISC-V platforms and operating systems that support the virtual memory systems and the two-stage address translations defined by the privileged specification. The IOMMU complements the RISC-V MMU capabilities defined by the privileged specification to provide similar address translation and protection functions for accesses from I/O devices. This will be a Non-ISA specification and will support the following capabilities listed in the IOMMU charter.