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  1. RISC-V Specification Lifecycle
  2. RVS-2708

RVA23

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      The RVA23 profiles are intended to align implementations of RISC-V 64-bit application processors to allow binary software ecosystems to rely on a a large set of guaranteed extensions and a small number of discoverable coarse-grain options. It is explicitly a non-goal of RVA23 to allow more hardware implementation flexibility by supporting only a minimal set of features and a large number of fine-grain extensions.

        1.
        		 [Inception] - Initial Infrastructure Setup Specification Acceptance Criteria Done Rafael Sene 15/May/24 0
        2.
        		 [Plan] - Develop Specification Plan Planning Acceptance Criteria Done Unassigned 07/Jun/24 0
        3.
        		 [Plan] - Governing Committee Approval (Informal) Approval Approval Not Required Rafael Sene 15/May/24 0
        4.
        		 [Plan] - Request ARC Review (consultative activity) ARC Review AR Review Not Required Rafael Sene 23/May/24 0
        5.
        		 [Plan] - Schedule Plan Presentation to Chairs Specification Acceptance Criteria Done Rafael Sene 15/May/24 0
        6.
        		 [Plan] - Present Plan to Chairs Specification Acceptance Criteria Done Unassigned 15/May/24 0
        7.
        		 [Plan] - Chairs Approval Approval Approved Rafael Sene 15/May/24 0
        8.
        		 [Plan] - Notify TSC Specification Acceptance Criteria Done Rafael Sene 15/May/24 0
        9.
        		 [Development] - Develop Specification Development Acceptance Criteria Done Rafael Sene 07/Jun/24 0
        10.
        		 [Development] - Internal Review Development Acceptance Criteria Done Rafael Sene 23/May/24 0
        11.
        		 [Development] - ARC Review (consultative activity) ARC Review AR Review Not Required Rafael Sene 23/May/24 0
        12.
        		 [Development] - Governing Committee Specification Stabilization Approval (Informal) Approval Approval Not Required Rafael Sene 15/May/24 0
        13.
        		 [Freeze] - Complete Documentation of New Instructions, State Changes, and ISA Alterations Freeze Acceptance Criteria Not Started Unassigned   0
        14.
        		 [Freeze] - Develop Opcode Support Freeze Acceptance Criteria Not Started Unassigned   0
        15.
        		 [Freeze] - Implement Simulator Support Freeze Acceptance Criteria Not Started Unassigned   0
        16.
        		 [Freeze] - Implement psABI Freeze Acceptance Criteria Not Started Unassigned   0
        17.
        		 [Freeze] - Develop Support for GCC Freeze Acceptance Criteria Not Started Unassigned   0
        18.
        		 [Freeze] - Develop Support for LLVM Freeze Acceptance Criteria Not Started Unassigned   0
        19.
        		 [Freeze] - Develop RISC-V Tests Freeze Acceptance Criteria Not Started Unassigned   0
        20.
        		 [Freeze] - Perform Input Testing Freeze Acceptance Criteria Not Started Unassigned   0
        21.
        		 [Freeze] - Add Support into the Sail Golden Model Freeze Acceptance Criteria Not Started Unassigned   0
        22.
        		 [Freeze] - Create Proof of Concept Freeze Acceptance Criteria Not Started Unassigned   0
        23.
        		 [Freeze] - ARC Review (required) ARC Review Not Started Unassigned   0
        24.
        		 [Freeze] - Ensure Compliance with RISC-V Specification Policies Approval Not Started Unassigned   0
        25.
        		 [Freeze] - Request Signoffs from Committee Chair Approval Not Started Unassigned   0
        26.
        		 [Freeze] - Request Signoff from RISC-V CTO Approval Not Started Unassigned   0

            Unassigned Unassigned
            rsene Rafael Sene
            Krste Asanovic Krste Asanovic
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              Created:
              Updated: