Specification Plan Presentation

The objective of this specification is to enhance the Reliability, Availability, and Serviceability (RAS) features of RISC-V System on a Chip (SoC) hardware. The specification aims to standardize the reporting and logging of errors through a dedicated memory-mapped register interface. This will serve multiple purposes:

1. Enable real-time error detection.
2. Provide capabilities to log detected errors with details such as their severity, nature, and location.
3. Configure pathways to report these errors to a designated handler component.
4. Support reporting of attempts to consume corrupted data by an ultimate consumer component.
5. Enable software-initiated error logging, reporting, and testing of error handlers.

Moreover, the specification is designed to offer maximal flexibility for implementing error-handling strategies and should be compatible with existing RAS frameworks defined by other industry standards, such as PCIe and CXL.

Deprecated Plan and Status:

Plan:

https://docs.google.com/spreadsheets/d/1OQQyuYdIh0IT1t9n7VbHeu_y0izEUANK5_cdC0TgXOg/edit#gid=257164574

Status:
https://docs.google.com/spreadsheets/d/1OQQyuYdIh0IT1t9n7VbHeu_y0izEUANK5_cdC0TgXOg/edit#gid=257164574