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Specification
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Resolution: Unresolved
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Medium
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ResNMI
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Yes
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ISA
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Smrnmi
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Ratification-Ready Approval Not Required
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Completed
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1
The base machine-level architecture supports only unresumable non-maskable interrupts (UNMIs), where the NMI jumps to a handler in machine mode, overwriting the current mepc and mcause register values. If the hart had been executing machine-mode code in a trap handler, the previous values in mepc and mcause would not be recoverable and so execution is not generally resumable.
The Smrnmi extension adds support for resumable non-maskable interrupts (RNMIs) to RISC-V. The extension adds four new CSRs (mnepc, mncause, mnstatus, and mnscratch) to hold the interrupted state, and one new instruction, MNRET, to resume from the RNMI handler.
Google Drive link for the extension: https://drive.google.com/file/d/1rz1GQSaEm6gSF2UN2jE2Md3_5BLdqd71/view
1.
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[Ratification-Ready] - Committee Chair Signoffs | Approval In Progress | Jeff Scheel | 04/Mar/24 | 4 | ||
2.
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[Ratification-Ready] - TSC Approval | Not Started | Jeff Scheel | 06/Mar/24 | 0 | ||
3.
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[Ratification-Ready] - Schedule BoD Review | Not Started | Rafael Sene | 27/Jun/24 | 0 | ||
4.
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[Ratification-Ready] - BoD Approval | Not Started | Rafael Sene | 27/Jun/24 | 0 |