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Type: Group
Resolution: Unresolved
Priority: Medium
Labels:
None

RVI Staff Action:
Not Required
Group Type:
Task Group (TG)
Groups.io:
https://lists.riscv.org/g/tech-debug
Charter:
https://github.com/riscv/riscv-debug-spec/
Chair:
Paul Donahue
Chair Email:
pdonahue@ventanamicro.com
Is Acting Chair?:
No
Chair Affiliation:
Ventana Micro Systems
Vice-Chair:
Tim Newsome
Vice-Chair Email:
tim@casualhacker.net
Is Acting Vice-Chair?:
No
Vice-chair Affiliation:
Individual Member

The Debug Task Group's goal is the creation of tasks groups which create specifications concerning for how to enable low-level hardware debugging on RISC-V implementations.

develops

RVS-981 Debug for Hardware Platforms

Specification in Ratification-Ready

is direct-lined by

RVG-88 SOC Infrastructure (HC)

Active

is dotted-lined by

RVG-104 Technology (HC)

Active

Assignee:: Unassigned

Reporter:: Rafael Sene

Votes:: 0 Vote for this issue

Watchers:: 2 Start watching this issue

Created:: 14/Jul/23 8:46 PM

Updated:: 11/Jan/24 9:40 PM

Group Creation Date:: 17/Dec/19

Chair Start Date:: 22/Mar/22

Chair End Date:: 16/Nov/24

Vice-Chair Start Date:: 22/Mar/22

Vice-chair End Date:: 16/Nov/24

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