The RISC-V Soft-CPU SIG provides a forum to advance RISC-V as the preeminent ecosystem for FPGA processor and SoC designs. The SIG will not deliver any specifications or standards. It will develop overall strategy and establish priorities, then create task groups to develop any identified outputs.

Background and Motivation

1. Today’s FPGA embedded systems platforms are unnecessarily siloed, proprietary, fragmented, and duplicative, whereas RISC-V standards can enable common, interoperable FPGA systems platform profiles.
2. RISC-V soft processors are an agile platform for rapid innovation in processor and system architecture and implementation.
3. There are at least as many distinct RISC-V soft processor cores as ASIC cores.
4. FPGA RISC-V systems bring new opportunities and challenges, such as late customizability / fine-grained subsetting, novel memory systems and interconnects, accelerator integration, partial reconfiguration, and alternative arithmetic systems, that may not be a priority or relevant to ASIC implementations.
5. Proposed RISC-V ISA extensions may inadvertently induce circuit structures that are prohibitively expensive in certain FPGA devices or use cases.
6. The shared interests and needs of diverse RISC-V FPGA users are better expressed from within a common technical community.

Goals and Scope

1. Provide a forum for FPGA vendors, developers, and users to pursue common interests, benchmarks, and develop community-based recommendations.
2. Represent FPGA implementation considerations within RISC-V TGs, acting as a resource for consultations and to monitor progress of RISC-V standards from the perspective of Soft CPUs.
3. Develop strategy, perform gap analysis, and propose RISC-V extensions, RISC-V platforms, RISC-V profiles, and other technical product for FPGA implementations and applications.
4. Promote FPGA SoftCPU IP development and inclusion in RISC-V International activities, publications and directories.

Leadership History

Period	Chair	Vice-Chair
2023-2024	Guy Lemieux <guy.lemieux@gmail.com>	Jan Gray <jan@fpga.org>